dc/hbj11: add hardware info
Change-Id: I34c3906e241117fe56ed903e7cd11f8b804d9e30
Reviewed-on: https://gerrit.hackerspace.pl/c/hscloud/+/1381
Reviewed-by: q3k <q3k@hackerspace.pl>
diff --git a/dc/hbj11/hardware/hbj11-footprints.pretty/cardedge.kicad_mod b/dc/hbj11/hardware/hbj11-footprints.pretty/cardedge.kicad_mod
new file mode 100644
index 0000000..9861248
--- /dev/null
+++ b/dc/hbj11/hardware/hbj11-footprints.pretty/cardedge.kicad_mod
@@ -0,0 +1,106 @@
+(module cardedge (layer F.Cu) (tedit 601544E0)
+ (fp_text reference REF** (at 0 -7 90) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value cardedge (at 0 -12 270) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (pad B1 smd rect (at 0 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B2 smd rect (at 1 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B3 smd rect (at 2 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B4 smd rect (at 3 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B5 smd rect (at 4 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B6 smd rect (at 5 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B7 smd rect (at 6 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B8 smd rect (at 7 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B9 smd rect (at 8 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B10 smd rect (at 9 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B11 smd rect (at 10 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B12 smd rect (at 13 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B13 smd rect (at 14 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B14 smd rect (at 15 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B15 smd rect (at 16 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B16 smd rect (at 17 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B17 smd rect (at 18 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B18 smd rect (at 19 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B19 smd rect (at 20 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B20 smd rect (at 21 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B21 smd rect (at 22 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B22 smd rect (at 23 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B23 smd rect (at 24 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B24 smd rect (at 25 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B25 smd rect (at 26 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B26 smd rect (at 27 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B27 smd rect (at 28 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B28 smd rect (at 29 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B29 smd rect (at 30 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B30 smd rect (at 31 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B31 smd rect (at 32 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B32 smd rect (at 33 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B33 smd rect (at 34 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B34 smd rect (at 35 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B35 smd rect (at 36 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B36 smd rect (at 37 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B37 smd rect (at 38 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B38 smd rect (at 39 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B39 smd rect (at 40 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B40 smd rect (at 41 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B41 smd rect (at 42 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B42 smd rect (at 43 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B43 smd rect (at 44 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B44 smd rect (at 45 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B45 smd rect (at 46 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B46 smd rect (at 47 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B47 smd rect (at 48 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B48 smd rect (at 49 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad B49 smd rect (at 50 -2) (size 0.7 4) (layers F.Cu F.Mask))
+ (pad A1 smd rect (at 0 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A2 smd rect (at 1 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A3 smd rect (at 2 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A4 smd rect (at 3 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A5 smd rect (at 4 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A6 smd rect (at 5 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A7 smd rect (at 6 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A8 smd rect (at 7 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A9 smd rect (at 8 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A10 smd rect (at 9 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A11 smd rect (at 10 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A12 smd rect (at 13 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A13 smd rect (at 14 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A14 smd rect (at 15 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A15 smd rect (at 16 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A16 smd rect (at 17 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A17 smd rect (at 18 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A18 smd rect (at 19 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A19 smd rect (at 20 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A20 smd rect (at 21 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A21 smd rect (at 22 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A22 smd rect (at 23 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A23 smd rect (at 24 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A24 smd rect (at 25 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A25 smd rect (at 26 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A26 smd rect (at 27 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A27 smd rect (at 28 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A28 smd rect (at 29 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A29 smd rect (at 30 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A30 smd rect (at 31 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A31 smd rect (at 32 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A32 smd rect (at 33 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A33 smd rect (at 34 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A34 smd rect (at 35 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A35 smd rect (at 36 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A36 smd rect (at 37 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A37 smd rect (at 38 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A38 smd rect (at 39 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A39 smd rect (at 40 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A40 smd rect (at 41 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A41 smd rect (at 42 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A42 smd rect (at 43 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A43 smd rect (at 44 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A44 smd rect (at 45 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A45 smd rect (at 46 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A46 smd rect (at 47 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A47 smd rect (at 48 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A48 smd rect (at 49 -2) (size 0.7 4) (layers B.Cu B.Mask))
+ (pad A49 smd rect (at 50 -2) (size 0.7 4) (layers B.Cu B.Mask))
+)