hacklock: init at rev a
Change-Id: Ic0481ae37ca354233658ff0d8d2a9b5d7c7a5a2a
Reviewed-on: https://gerrit.hackerspace.pl/c/hscloud/+/1525
Reviewed-by: q3k <q3k@hackerspace.pl>
diff --git a/hswaw/hacklock/hardware/hacklock-2137/fab1/hacklock2137-rev-a/hacklock-2137-F_Cu.gbr b/hswaw/hacklock/hardware/hacklock-2137/fab1/hacklock2137-rev-a/hacklock-2137-F_Cu.gbr
new file mode 100644
index 0000000..7d61663
--- /dev/null
+++ b/hswaw/hacklock/hardware/hacklock-2137/fab1/hacklock2137-rev-a/hacklock-2137-F_Cu.gbr
@@ -0,0 +1,4246 @@
+%TF.GenerationSoftware,KiCad,Pcbnew,7.0.0*%
+%TF.CreationDate,2023-06-21T13:32:25+02:00*%
+%TF.ProjectId,hacklock-2137,6861636b-6c6f-4636-9b2d-323133372e6b,rev?*%
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+G04 Created by KiCad (PCBNEW 7.0.0) date 2023-06-21 13:32:25*
+%MOMM*%
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+G01*
+G04 APERTURE LIST*
+G04 Aperture macros list*
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+0 Rectangle with rounded corners*
+0 $1 Rounding radius*
+0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
+0 Add a 4 corners polygon primitive as box body*
+4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
+0 Add four circle primitives for the rounded corners*
+1,1,$1+$1,$2,$3*
+1,1,$1+$1,$4,$5*
+1,1,$1+$1,$6,$7*
+1,1,$1+$1,$8,$9*
+0 Add four rect primitives between the rounded corners*
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+%TO.N,/UART1_TX_5V*%
+X124312500Y-73035000D03*
+%TO.P,U5,12,R1OUT*%
+%TO.N,Net-(U5-R1OUT)*%
+X124312500Y-71765000D03*
+%TO.P,U5,13,R1IN*%
+%TO.N,/RS232_1_RX*%
+X124312500Y-70495000D03*
+%TO.P,U5,14,T1OUT*%
+%TO.N,/RS232_1_TX*%
+X124312500Y-69225000D03*
+%TO.P,U5,15,GND*%
+%TO.N,GND*%
+X124312500Y-67955000D03*
+%TO.P,U5,16,VCC*%
+%TO.N,+5V*%
+X124312500Y-66685000D03*
+%TD*%
+D19*
+%TO.P,U4,1,A1*%
+%TO.N,/UART1_TX*%
+X119000000Y-81000000D03*
+%TO.P,U4,2,VCCA*%
+%TO.N,+3V3*%
+X119000000Y-81650000D03*
+%TO.P,U4,3,A2*%
+%TO.N,Net-(U4-A2)*%
+X119000000Y-82300000D03*
+%TO.P,U4,4,A3*%
+%TO.N,/UART2_TX*%
+X119000000Y-82950000D03*
+%TO.P,U4,5,A4*%
+%TO.N,Net-(U4-A4)*%
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+%TO.N,unconnected-(U4-A5-Pad6)*%
+X119000000Y-84250000D03*
+%TO.P,U4,7,A6*%
+%TO.N,unconnected-(U4-A6-Pad7)*%
+X119000000Y-84900000D03*
+%TO.P,U4,8,A7*%
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+%TO.N,unconnected-(U4-A8-Pad9)*%
+X119000000Y-86200000D03*
+%TO.P,U4,10,OE*%
+%TO.N,+3V3*%
+X119000000Y-86850000D03*
+%TO.P,U4,11,GND*%
+%TO.N,GND*%
+X124725000Y-86850000D03*
+%TO.P,U4,12,B8*%
+%TO.N,unconnected-(U4-B8-Pad12)*%
+X124725000Y-86200000D03*
+%TO.P,U4,13,B7*%
+%TO.N,unconnected-(U4-B7-Pad13)*%
+X124725000Y-85550000D03*
+%TO.P,U4,14,B6*%
+%TO.N,unconnected-(U4-B6-Pad14)*%
+X124725000Y-84900000D03*
+%TO.P,U4,15,B5*%
+%TO.N,unconnected-(U4-B5-Pad15)*%
+X124725000Y-84250000D03*
+%TO.P,U4,16,B4*%
+%TO.N,/UART2_RX_5V*%
+X124725000Y-83600000D03*
+%TO.P,U4,17,B3*%
+%TO.N,/UART2_TX_5V*%
+X124725000Y-82950000D03*
+%TO.P,U4,18,B2*%
+%TO.N,/UART1_RX_5V*%
+X124725000Y-82300000D03*
+%TO.P,U4,19,VCCB*%
+%TO.N,+5V*%
+X124725000Y-81650000D03*
+%TO.P,U4,20,B1*%
+%TO.N,/UART1_TX_5V*%
+X124725000Y-81000000D03*
+%TD*%
+D20*
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+%TO.N,+5V*%
+X99274999Y-83149999D03*
+%TO.P,U3,2,VO*%
+%TO.N,+3V3*%
+X96974999Y-83149999D03*
+D21*
+X96974999Y-76849999D03*
+D20*
+%TO.P,U3,1,GND*%
+%TO.N,GND*%
+X94674999Y-83149999D03*
+%TD*%
+D22*
+%TO.P,U2,3,VO*%
+%TO.N,+5V*%
+X85039999Y-85729999D03*
+%TO.P,U2,2,GND*%
+%TO.N,GND*%
+X82499999Y-85729999D03*
+D23*
+%TO.P,U2,1,VI*%
+%TO.N,+24V*%
+X79959999Y-85729999D03*
+%TD*%
+D24*
+%TO.P,U1,41,GND*%
+%TO.N,GND*%
+X198809999Y-75099999D03*
+X201609999Y-76499999D03*
+X198809999Y-77899999D03*
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+X201609999Y-76499999D03*
+X198809999Y-75099999D03*
+X200209999Y-75099999D03*
+X201609999Y-75099999D03*
+D25*
+%TO.P,U1,40,GND*%
+X207929999Y-86749999D03*
+%TO.P,U1,39,GPIO1/TOUCH1/ADC1_CH0*%
+%TO.N,/PWR1_FB*%
+X206659999Y-86749999D03*
+%TO.P,U1,38,GPIO2/TOUCH2/ADC1_CH1*%
+%TO.N,/PWR2_FB*%
+X205389999Y-86749999D03*
+%TO.P,U1,37,U0TXD/GPIO43/CLK_OUT1*%
+%TO.N,/UART0_TX*%
+X204119999Y-86749999D03*
+%TO.P,U1,36,U0RXD/GPIO44/CLK_OUT2*%
+%TO.N,/UART0_RX*%
+X202849999Y-86749999D03*
+%TO.P,U1,35,MTMS/GPIO42*%
+%TO.N,unconnected-(U1-MTMS{slash}GPIO42-Pad35)*%
+X201579999Y-86749999D03*
+%TO.P,U1,34,MTDI/GPIO41/CLK_OUT1*%
+%TO.N,unconnected-(U1-MTDI{slash}GPIO41{slash}CLK_OUT1-Pad34)*%
+X200309999Y-86749999D03*
+%TO.P,U1,33,MTDO/GPIO40/CLK_OUT2*%
+%TO.N,unconnected-(U1-MTDO{slash}GPIO40{slash}CLK_OUT2-Pad33)*%
+X199039999Y-86749999D03*
+%TO.P,U1,32,MTCK/GPIO39/CLK_OUT3/SUBSPICS1*%
+%TO.N,unconnected-(U1-MTCK{slash}GPIO39{slash}CLK_OUT3{slash}SUBSPICS1-Pad32)*%
+X197769999Y-86749999D03*
+%TO.P,U1,31,GPIO38/FSPIWP/SUBSPIWP*%
+%TO.N,/I2C_SCL*%
+X196499999Y-86749999D03*
+%TO.P,U1,30,SPIDQS/GPIO37/FSPIQ/SUBSPIQ*%
+%TO.N,unconnected-(U1-SPIDQS{slash}GPIO37{slash}FSPIQ{slash}SUBSPIQ-Pad30)*%
+X195229999Y-86749999D03*
+%TO.P,U1,29,SPIIO7/GPIO36/FSPICLK/SUBSPICLK*%
+%TO.N,unconnected-(U1-SPIIO7{slash}GPIO36{slash}FSPICLK{slash}SUBSPICLK-Pad29)*%
+X193959999Y-86749999D03*
+%TO.P,U1,28,SPIIO6/GPIO35/FSPID/SUBSPID*%
+%TO.N,unconnected-(U1-SPIIO6{slash}GPIO35{slash}FSPID{slash}SUBSPID-Pad28)*%
+X192689999Y-86749999D03*
+%TO.P,U1,27,GPIO0/BOOT*%
+%TO.N,Net-(SW1-A)*%
+X191419999Y-86749999D03*
+D26*
+%TO.P,U1,26,GPIO45*%
+%TO.N,unconnected-(U1-GPIO45-Pad26)*%
+X190169999Y-84984999D03*
+%TO.P,U1,25,GPIO48/SPICLK_N/SUBSPICLK_N_DIFF*%
+%TO.N,/WS2812*%
+X190169999Y-83714999D03*
+%TO.P,U1,24,GPIO47/SPICLK_P/SUBSPICLK_P_DIFF*%
+%TO.N,/I2C_SDA*%
+X190169999Y-82444999D03*
+%TO.P,U1,23,GPIO21*%
+%TO.N,/OUT21_3V3*%
+X190169999Y-81174999D03*
+%TO.P,U1,22,GPIO14/TOUCH14/ADC2_CH3/FSPIWP/FSPIDQS/SUBSPIWP*%
+%TO.N,/OUT14_3V3*%
+X190169999Y-79904999D03*
+%TO.P,U1,21,GPIO13/TOUCH13/ADC2_CH2/FSPIQ/FSPIIO7/SUBSPIQ*%
+%TO.N,/OUT13_3V3*%
+X190169999Y-78634999D03*
+%TO.P,U1,20,GPIO12/TOUCH12/ADC2_CH1/FSPICLK/FSPIIO6/SUBSPICLK*%
+%TO.N,/OUT12_3V3*%
+X190169999Y-77364999D03*
+%TO.P,U1,19,GPIO11/TOUCH11/ADC2_CH0/FSPID/FSPIIO5/SUBSPID*%
+%TO.N,/IN11_3V3*%
+X190169999Y-76094999D03*
+%TO.P,U1,18,GPIO10/TOUCH10/ADC1_CH9/FSPICS0/FSPIIO4/SUBSPICS0*%
+%TO.N,/IN10_3V3*%
+X190169999Y-74824999D03*
+%TO.P,U1,17,GPIO9/TOUCH9/ADC1_CH8/FSPIHD/SUBSPIHD*%
+%TO.N,/UART2_RS232_EN*%
+X190169999Y-73554999D03*
+%TO.P,U1,16,GPIO46*%
+%TO.N,unconnected-(U1-GPIO46-Pad16)*%
+X190169999Y-72284999D03*
+%TO.P,U1,15,GPIO3/TOUCH3/ADC1_CH2*%
+%TO.N,unconnected-(U1-GPIO3{slash}TOUCH3{slash}ADC1_CH2-Pad15)*%
+X190169999Y-71014999D03*
+D25*
+%TO.P,U1,14,GPIO20/U1CTS/ADC2_CH9/CLK_OUT1/USB_D+*%
+%TO.N,/D+*%
+X191419999Y-69249999D03*
+%TO.P,U1,13,GPIO19/U1RTS/ADC2_CH8/CLK_OUT2/USB_D-*%
+%TO.N,/D-*%
+X192689999Y-69249999D03*
+%TO.P,U1,12,GPIO8/TOUCH8/ADC1_CH7/SUBSPICS1*%
+%TO.N,/UART1_RS232_EN*%
+X193959999Y-69249999D03*
+%TO.P,U1,11,GPIO18/U1RXD/ADC2_CH7/CLK_OUT3*%
+%TO.N,/UART1_RX*%
+X195229999Y-69249999D03*
+%TO.P,U1,10,GPIO17/U1TXD/ADC2_CH6*%
+%TO.N,/UART1_TX*%
+X196499999Y-69249999D03*
+%TO.P,U1,9,GPIO16/U0CTS/ADC2_CH5/XTAL_32K_N*%
+%TO.N,unconnected-(U1-GPIO16{slash}U0CTS{slash}ADC2_CH5{slash}XTAL_32K_N-Pad9)*%
+X197769999Y-69249999D03*
+%TO.P,U1,8,GPIO15/U0RTS/ADC2_CH4/XTAL_32K_P*%
+%TO.N,unconnected-(U1-GPIO15{slash}U0RTS{slash}ADC2_CH4{slash}XTAL_32K_P-Pad8)*%
+X199039999Y-69249999D03*
+%TO.P,U1,7,GPIO7/TOUCH7/ADC1_CH6*%
+%TO.N,/UART2_5V_EN*%
+X200309999Y-69249999D03*
+%TO.P,U1,6,GPIO6/TOUCH6/ADC1_CH5*%
+%TO.N,/UART1_5V_EN*%
+X201579999Y-69249999D03*
+%TO.P,U1,5,GPIO5/TOUCH5/ADC1_CH4*%
+%TO.N,/UART2_RX*%
+X202849999Y-69249999D03*
+%TO.P,U1,4,GPIO4/TOUCH4/ADC1_CH3*%
+%TO.N,/UART2_TX*%
+X204119999Y-69249999D03*
+%TO.P,U1,3,EN*%
+%TO.N,/RST*%
+X205389999Y-69249999D03*
+%TO.P,U1,2,3V3*%
+%TO.N,+3V3*%
+X206659999Y-69249999D03*
+%TO.P,U1,1,GND*%
+%TO.N,GND*%
+X207929999Y-69249999D03*
+%TD*%
+D27*
+%TO.P,SW2,1,A*%
+%TO.N,/RST*%
+X201349999Y-100599999D03*
+X207649999Y-100599999D03*
+%TO.P,SW2,2,B*%
+%TO.N,GND*%
+X207649999Y-104399999D03*
+X201349999Y-104399999D03*
+%TD*%
+%TO.P,SW1,1,A*%
+%TO.N,Net-(SW1-A)*%
+X201349999Y-92599999D03*
+X207649999Y-92599999D03*
+%TO.P,SW1,2,B*%
+%TO.N,GND*%
+X207649999Y-96399999D03*
+X201349999Y-96399999D03*
+%TD*%
+D11*
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+%TO.N,+3V3*%
+X194000000Y-98990000D03*
+%TO.P,R35,2*%
+%TO.N,Net-(J15-Pin_3)*%
+X194000000Y-100010000D03*
+%TD*%
+D28*
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+%TO.N,/I2C_SCL*%
+X101675000Y-103555000D03*
+%TO.P,R34,1*%
+%TO.N,+3V3*%
+X103325000Y-103555000D03*
+%TD*%
+D29*
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+%TO.N,+3V3*%
+X105175000Y-103555000D03*
+%TO.P,R33,2*%
+%TO.N,/I2C_SDA*%
+X106825000Y-103555000D03*
+%TD*%
+D11*
+%TO.P,R32,1*%
+%TO.N,GND*%
+X154500000Y-94045000D03*
+%TO.P,R32,2*%
+%TO.N,Net-(Q2-B)*%
+X154500000Y-95065000D03*
+%TD*%
+%TO.P,R31,1*%
+%TO.N,/OUT21_3V3*%
+X155500000Y-94045000D03*
+%TO.P,R31,2*%
+%TO.N,Net-(Q2-B)*%
+X155500000Y-95065000D03*
+%TD*%
+%TO.P,R30,1*%
+%TO.N,Net-(D21-K)*%
+X154500000Y-92045000D03*
+%TO.P,R30,2*%
+%TO.N,GND*%
+X154500000Y-93065000D03*
+%TD*%
+%TO.P,R29,1*%
+%TO.N,Net-(D19-K)*%
+X170500000Y-92045000D03*
+%TO.P,R29,2*%
+%TO.N,GND*%
+X170500000Y-93065000D03*
+%TD*%
+%TO.P,R28,1*%
+%TO.N,GND*%
+X170500000Y-94035000D03*
+%TO.P,R28,2*%
+%TO.N,Net-(Q1-B)*%
+X170500000Y-95055000D03*
+%TD*%
+%TO.P,R27,1*%
+%TO.N,/OUT14_3V3*%
+X171500000Y-94045000D03*
+%TO.P,R27,2*%
+%TO.N,Net-(Q1-B)*%
+X171500000Y-95065000D03*
+%TD*%
+%TO.P,R26,2*%
+%TO.N,GND*%
+X191500000Y-92065000D03*
+%TO.P,R26,1*%
+%TO.N,Net-(D18-K)*%
+X191500000Y-91045000D03*
+%TD*%
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+%TO.N,GND*%
+X182000000Y-92065000D03*
+%TO.P,R25,1*%
+%TO.N,Net-(D17-K)*%
+X182000000Y-91045000D03*
+%TD*%
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+%TO.N,Net-(D16-A)*%
+X130000000Y-91045000D03*
+%TO.P,R24,2*%
+%TO.N,+3V3*%
+X130000000Y-92065000D03*
+%TD*%
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+%TO.N,Net-(D15-A)*%
+X120500000Y-91045000D03*
+%TO.P,R23,2*%
+%TO.N,+3V3*%
+X120500000Y-92065000D03*
+%TD*%
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+%TO.N,Net-(D14-K)*%
+X148000000Y-78480000D03*
+%TO.P,R22,2*%
+%TO.N,GND*%
+X148000000Y-79500000D03*
+%TD*%
+D30*
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+%TO.N,Net-(D13-K)*%
+X148000000Y-81500000D03*
+%TO.P,R21,2*%
+%TO.N,GND*%
+X148000000Y-80480000D03*
+%TD*%
+D11*
+%TO.P,R20,1*%
+%TO.N,Net-(D12-K)*%
+X157000000Y-78480000D03*
+%TO.P,R20,2*%
+%TO.N,GND*%
+X157000000Y-79500000D03*
+%TD*%
+D30*
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+%TO.N,Net-(D11-K)*%
+X157000000Y-81500000D03*
+%TO.P,R19,2*%
+%TO.N,GND*%
+X157000000Y-80480000D03*
+%TD*%
+D31*
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+%TO.N,Net-(C10-Pad1)*%
+X126500000Y-102430000D03*
+%TO.P,R18,2*%
+%TO.N,GND*%
+X126500000Y-104080000D03*
+%TD*%
+D32*
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+%TO.N,Net-(C10-Pad1)*%
+X128000000Y-102430000D03*
+%TO.P,R17,1*%
+%TO.N,/IN11_24V*%
+X128000000Y-104080000D03*
+%TD*%
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+X123500000Y-104080000D03*
+%TO.P,R16,2*%
+%TO.N,Net-(C9-Pad1)*%
+X123500000Y-102430000D03*
+%TD*%
+D31*
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+%TO.N,Net-(C9-Pad1)*%
+X122000000Y-102430000D03*
+%TO.P,R15,2*%
+%TO.N,GND*%
+X122000000Y-104080000D03*
+%TD*%
+D33*
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+%TO.N,Net-(J1-D+-PadA6)*%
+X199510000Y-59000000D03*
+%TO.P,R14,2*%
+%TO.N,/D+*%
+X198490000Y-59000000D03*
+%TD*%
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+X198490000Y-60000000D03*
+%TO.P,R13,1*%
+%TO.N,Net-(J1-D--PadA7)*%
+X199510000Y-60000000D03*
+%TD*%
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+%TO.N,/PWR2*%
+X62770000Y-66500000D03*
+%TO.P,R12,2*%
+%TO.N,Net-(D9-A)*%
+X61750000Y-66500000D03*
+%TD*%
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+%TO.N,Net-(D8-A)*%
+X61750000Y-68500000D03*
+%TO.P,R11,1*%
+%TO.N,/PWR1*%
+X62770000Y-68500000D03*
+%TD*%
+D10*
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+%TO.N,GND*%
+X89000000Y-100000000D03*
+%TO.P,R10,1*%
+%TO.N,/PWR2_FB*%
+X87980000Y-100000000D03*
+%TD*%
+%TO.P,R9,2*%
+%TO.N,/PWR2_FB*%
+X87000000Y-100000000D03*
+%TO.P,R9,1*%
+%TO.N,/PWR2*%
+X85980000Y-100000000D03*
+%TD*%
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+X87980000Y-99000000D03*
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+%TO.N,GND*%
+X89000000Y-99000000D03*
+%TD*%
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+%TO.N,/PWR1_FB*%
+X86990000Y-99000000D03*
+%TO.P,R7,1*%
+%TO.N,/PWR1*%
+X85970000Y-99000000D03*
+%TD*%
+D30*
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+%TO.N,+3V3*%
+X199500000Y-101500000D03*
+%TO.P,R6,2*%
+%TO.N,/RST*%
+X199500000Y-100480000D03*
+%TD*%
+D33*
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+%TO.N,Net-(J1-CC2)*%
+X199510000Y-58000000D03*
+%TO.P,R5,2*%
+%TO.N,GND*%
+X198490000Y-58000000D03*
+%TD*%
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+%TO.N,Net-(J1-CC1)*%
+X199510000Y-61000000D03*
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+%TO.N,GND*%
+X198490000Y-61000000D03*
+%TD*%
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+%TO.N,+3V3*%
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+%TO.N,Net-(D3-A)*%
+X61740000Y-60500000D03*
+%TD*%
+%TO.P,R2,1*%
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+X62760000Y-62500000D03*
+%TO.P,R2,2*%
+%TO.N,Net-(D2-A)*%
+X61740000Y-62500000D03*
+%TD*%
+%TO.P,R1,1*%
+%TO.N,+24V*%
+X62770000Y-64500000D03*
+%TO.P,R1,2*%
+%TO.N,Net-(D1-A)*%
+X61750000Y-64500000D03*
+%TD*%
+D34*
+%TO.P,Q2,1,B*%
+%TO.N,Net-(Q2-B)*%
+X152375000Y-95505000D03*
+%TO.P,Q2,2,E*%
+%TO.N,GND*%
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+%TD*%
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+%TD*%
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+%TO.P,D22,2,A*%
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+%TD*%
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+%TD*%
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+%TD*%
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+%TD*%
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+%TO.P,D17,1,K*%
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+%TD*%
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+%TO.P,D16,2,A*%
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+%TD*%
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+%TO.P,D15,2,A*%
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+%TD*%
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+%TD*%
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+%TD*%
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+%TD*%
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+%TD*%
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+%TD*%
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+%TD*%
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+%TD*%
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+%TO.P,D7,2,A*%
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+%TD*%
+D54*
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+%TO.N,/PWR2*%
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+%TD*%
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+%TD*%
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+%TO.P,D1,2,A*%
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+%TD*%
+D55*
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+%TO.P,C17,1*%
+%TO.N,+5V*%
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+%TD*%
+D14*
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+%TO.P,C16,2*%
+%TO.N,GND*%
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+%TD*%
+D56*
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+%TO.P,C15,1*%
+%TO.N,+24V*%
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+%TD*%
+D55*
+%TO.P,C14,1*%
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+X72330000Y-89830000D01*
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+%TO.N,/PWR1*%
+X62770000Y-68500000D02*
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+X66000000Y-69500000D01*
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+X66500000Y-99500000D01*
+%TO.N,/PWR2*%
+X62770000Y-66500000D02*
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+X65000000Y-66500000D02*
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+%TO.N,/PWR1*%
+X72185000Y-103185000D02*
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+X70500000Y-101500000D02*
+X72185000Y-103185000D01*
+%TO.N,/PWR1_FB*%
+X194500000Y-84500000D02*
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+X206660000Y-85915000D01*
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+X206660000Y-86750000D01*
+%TO.N,/OUT21_3V3*%
+X184000000Y-88500000D02*
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+X195000000Y-85400498D02*
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+X205390000Y-85750000D01*
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+X205390000Y-86750000D01*
+%TO.N,Net-(D16-A)*%
+X128437500Y-91555000D02*
+X129490000Y-91555000D01*
+X129490000Y-91555000D02*
+X130000000Y-91045000D01*
+%TO.N,Net-(D15-A)*%
+X122062500Y-91555000D02*
+X121010000Y-91555000D01*
+X121010000Y-91555000D02*
+X120500000Y-91045000D01*
+%TO.N,/UART2_RX*%
+X150675000Y-77500000D02*
+X151675000Y-76500000D01*
+X145601500Y-78500000D02*
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+X151675000Y-78752500D02*
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+X135500000Y-78650500D01*
+X146601500Y-77500000D02*
+X150675000Y-77500000D01*
+%TO.N,Net-(U5-R1OUT)*%
+X123677244Y-71765000D02*
+X121471122Y-73971122D01*
+X124312500Y-71765000D02*
+X123677244Y-71765000D01*
+%TO.N,/UART1_RX_5V*%
+X126500000Y-76500000D02*
+X126500000Y-81800000D01*
+X126500000Y-81800000D02*
+X127000000Y-82300000D01*
+%TO.N,/UART2_TX_5V*%
+X122224500Y-74775500D02*
+X122224500Y-76837298D01*
+X122500000Y-74500000D02*
+X122224500Y-74775500D01*
+%TO.N,/UART1_TX_5V*%
+X124725000Y-81000000D02*
+X124725000Y-80424195D01*
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+X121500000Y-77199195D01*
+X123431842Y-73035000D02*
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+X121500000Y-77199195D02*
+X121500000Y-74966842D01*
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+X123431842Y-73035000D01*
+%TO.N,Net-(U4-A4)*%
+X117500000Y-87869000D02*
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+X128500000Y-87450097D02*
+X129461821Y-86488276D01*
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+X129461821Y-86488276D02*
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+X115131000Y-84369000D02*
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+X131541610Y-84017012D02*
+X130512299Y-82987701D01*
+X131541610Y-87435462D02*
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+X119000000Y-83600000D02*
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+%TO.N,/UART2_TX*%
+X131000000Y-88275500D02*
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+X134433684Y-88500000D01*
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+X145275500Y-85500000D01*
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+X115783158Y-87716842D01*
+X128500000Y-88246000D02*
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+X129487701Y-87487701D01*
+X150138000Y-82289500D02*
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+X114754000Y-84500000D02*
+X114754000Y-86687684D01*
+X115783158Y-87716842D02*
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+X128500000Y-88246000D01*
+X149500000Y-82289500D02*
+X150138000Y-82289500D01*
+%TO.N,/UART1_TX*%
+X152500000Y-85775500D02*
+X152275500Y-86000000D01*
+X152275500Y-86000000D02*
+X137466842Y-86000000D01*
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+X114000000Y-83405342D01*
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+X119000000Y-81000000D01*
+%TO.N,Net-(U4-A2)*%
+X119000000Y-82300000D02*
+X115638500Y-82300000D01*
+X116156158Y-88623000D02*
+X129377000Y-88623000D01*
+X115638500Y-82300000D02*
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+X116156158Y-88623000D01*
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+X130500000Y-87500000D01*
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+X130500000Y-84000000D01*
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+X129500000Y-83000000D01*
+%TO.N,/UART2_TX*%
+X114754000Y-83746000D02*
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+X115550000Y-82950000D02*
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+X119000000Y-82950000D02*
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+%TO.N,/UART1_TX*%
+X152500000Y-82398500D02*
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+X153359738Y-82166512D01*
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+X153359738Y-81192762D01*
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+%TO.N,Net-(C10-Pad1)*%
+X128000000Y-102430000D02*
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+X129500000Y-102600000D01*
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+%TO.N,Net-(C9-Pad1)*%
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+X124830000Y-102430000D01*
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+X125000000Y-102600000D01*
+X122000000Y-102430000D02*
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+D65*
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+X189285000Y-111367500D02*
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+X185230000Y-102230000D01*
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+X184525000Y-102230000D01*
+%TO.N,/OUT12_24V*%
+X184205000Y-111367500D02*
+X184205000Y-103820000D01*
+X184205000Y-103820000D02*
+X184525000Y-103500000D01*
+D63*
+%TO.N,/UART1_TX_5V*%
+X182880000Y-53732500D02*
+X182880000Y-55620000D01*
+X127000000Y-70066316D02*
+X127000000Y-72525305D01*
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+X175402158Y-63131000D01*
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+X124777500Y-73500000D01*
+X124777500Y-73500000D02*
+X124312500Y-73035000D01*
+%TO.N,/UART1_RX_5V*%
+X126000000Y-72500000D02*
+X126500000Y-72000000D01*
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+X126500000Y-70033158D01*
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+X177800000Y-60200000D01*
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+X177800000Y-53732500D01*
+X127000000Y-82300000D02*
+X128200000Y-82300000D01*
+X124725000Y-82300000D02*
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+D62*
+%TO.N,+5V*%
+X133550000Y-76190000D02*
+X131610000Y-76190000D01*
+X131610000Y-76190000D02*
+X131530000Y-76110000D01*
+%TO.N,+3V3*%
+X133550000Y-74920000D02*
+X131720000Y-74920000D01*
+X131720000Y-74920000D02*
+X131530000Y-75110000D01*
+D63*
+%TO.N,/UART1_RX_5V*%
+X128200000Y-82300000D02*
+X131125000Y-79375000D01*
+X131125000Y-79375000D02*
+X137855000Y-79375000D01*
+X137855000Y-79375000D02*
+X138500000Y-78730000D01*
+%TO.N,/UART2_RX_5V*%
+X124725000Y-83600000D02*
+X127666579Y-83600000D01*
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+X129266579Y-82000000D01*
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+X140500000Y-82000000D01*
+X140500000Y-82000000D02*
+X141000000Y-82500000D01*
+%TO.N,/UART1_5V_EN*%
+X188000000Y-72500000D02*
+X187633000Y-72867000D01*
+X187633000Y-72867000D02*
+X185756000Y-72867000D01*
+X144877000Y-74810683D02*
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+X185756000Y-72867000D02*
+X184000000Y-74623000D01*
+X184000000Y-74623000D02*
+X167843841Y-74623000D01*
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+X147033158Y-84000000D01*
+X147033158Y-84000000D02*
+X144877000Y-81843842D01*
+X144877000Y-81843842D02*
+X144877000Y-74810683D01*
+%TO.N,/UART2_RX_5V*%
+X143000000Y-79000000D02*
+X143000000Y-78000000D01*
+X143000000Y-78000000D02*
+X143500000Y-77500000D01*
+X143500000Y-77500000D02*
+X143500000Y-75033158D01*
+X143500000Y-75033158D02*
+X142116842Y-73650000D01*
+X142116842Y-73650000D02*
+X138500000Y-73650000D01*
+%TO.N,/UART2_TX_5V*%
+X122695000Y-74305000D02*
+X122500000Y-74500000D01*
+X124312500Y-74305000D02*
+X122695000Y-74305000D01*
+%TO.N,Net-(U5-C2+)*%
+X117005000Y-70495000D02*
+X116500000Y-71000000D01*
+X119362500Y-70495000D02*
+X117005000Y-70495000D01*
+X116500000Y-71980000D02*
+X116520000Y-72000000D01*
+X116500000Y-71000000D02*
+X116500000Y-71980000D01*
+%TO.N,Net-(U5-C1+)*%
+X115500000Y-67000000D02*
+X115500000Y-68500000D01*
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+X116000000Y-69000000D01*
+X119362500Y-66685000D02*
+X115815000Y-66685000D01*
+X115815000Y-66685000D02*
+X115500000Y-67000000D01*
+X116000000Y-69000000D02*
+X116520000Y-69000000D01*
+%TO.N,Net-(U5-VS-)*%
+X117480000Y-73000000D02*
+X119327500Y-73000000D01*
+X119327500Y-73000000D02*
+X119362500Y-73035000D01*
+%TO.N,Net-(U5-C2-)*%
+X117480000Y-72000000D02*
+X119127500Y-72000000D01*
+X119127500Y-72000000D02*
+X119362500Y-71765000D01*
+%TO.N,Net-(U5-C1-)*%
+X117480000Y-69000000D02*
+X119137500Y-69000000D01*
+X119137500Y-69000000D02*
+X119362500Y-69225000D01*
+%TO.N,Net-(U5-VS+)*%
+X117480000Y-68000000D02*
+X119317500Y-68000000D01*
+X119317500Y-68000000D02*
+X119362500Y-67955000D01*
+%TO.N,/RS232_1_TX*%
+X124312500Y-69225000D02*
+X126241842Y-69225000D01*
+X126241842Y-69225000D02*
+X133466842Y-62000000D01*
+X133466842Y-62000000D02*
+X146237173Y-62000000D01*
+X146237173Y-62000000D02*
+X149675000Y-58562173D01*
+X149675000Y-58562173D02*
+X149675000Y-56325331D01*
+%TO.N,/RS232_1_RX*%
+X124312500Y-70495000D02*
+X125505000Y-70495000D01*
+X125505000Y-70495000D02*
+X133623000Y-62377000D01*
+X133623000Y-62377000D02*
+X146393331Y-62377000D01*
+X146393331Y-62377000D02*
+X152445000Y-56325331D01*
+%TO.N,/WS2812*%
+X189009500Y-83715000D02*
+X190170000Y-83715000D01*
+X187724500Y-85000000D02*
+X189009500Y-83715000D01*
+X181000000Y-82200000D02*
+X182200000Y-82200000D01*
+X182200000Y-82200000D02*
+X183500000Y-83500000D01*
+%TO.N,/UART1_RS232_EN*%
+X146000000Y-80000000D02*
+X145601500Y-80000000D01*
+X146326500Y-80326500D02*
+X146000000Y-80000000D01*
+X146326500Y-81673500D02*
+X146326500Y-80326500D01*
+X143000000Y-80500000D02*
+X139000000Y-80500000D01*
+X146049737Y-81950263D02*
+X146326500Y-81673500D01*
+X158246000Y-83123000D02*
+X156000000Y-83123000D01*
+X158500000Y-82869000D02*
+X158246000Y-83123000D01*
+X156000000Y-83123000D02*
+X147222474Y-83123000D01*
+X147222474Y-83123000D02*
+X146049737Y-81950263D01*
+X139000000Y-80500000D02*
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+X167500000Y-73869000D02*
+X158500000Y-82869000D01*
+X186500000Y-71000000D02*
+X183631000Y-73869000D01*
+X183631000Y-73869000D02*
+X167500000Y-73869000D01*
+X188000000Y-71000000D02*
+X186500000Y-71000000D01*
+%TO.N,/UART1_RX*%
+X154000000Y-85275500D02*
+X153724500Y-85000000D01*
+X146966841Y-85000000D02*
+X144123000Y-82156159D01*
+X153724500Y-85000000D02*
+X146966841Y-85000000D01*
+X144123000Y-82156159D02*
+X144123000Y-75123000D01*
+X144123000Y-75123000D02*
+X142025000Y-73025000D01*
+X142025000Y-73025000D02*
+X134195000Y-73025000D01*
+X134195000Y-73025000D02*
+X133550000Y-72380000D01*
+%TO.N,/UART2_5V_EN*%
+X187000000Y-72142500D02*
+X185947342Y-72142500D01*
+X185947342Y-72142500D02*
+X183843842Y-74246000D01*
+X183843842Y-74246000D02*
+X167687683Y-74246000D01*
+X167687683Y-74246000D02*
+X158433684Y-83500000D01*
+X158433684Y-83500000D02*
+X147066316Y-83500000D01*
+X147066316Y-83500000D02*
+X145283158Y-81716842D01*
+X145283158Y-81716842D02*
+X145601500Y-81398500D01*
+X145601500Y-81398500D02*
+X145601500Y-81000000D01*
+%TO.N,/UART1_RS232_EN*%
+X193960000Y-70540000D02*
+X193500000Y-71000000D01*
+X193960000Y-69250000D02*
+X193960000Y-70540000D01*
+X193500000Y-71000000D02*
+X193000000Y-71000000D01*
+%TO.N,/UART2_5V_EN*%
+X200310000Y-70313000D02*
+X198500000Y-72123000D01*
+X200310000Y-69250000D02*
+X200310000Y-70313000D01*
+X196000000Y-72123000D02*
+X194847500Y-72123000D01*
+X194847500Y-72123000D02*
+X194500000Y-71775500D01*
+X198500000Y-72123000D02*
+X196000000Y-72123000D01*
+X135050000Y-81500000D02*
+X133550000Y-80000000D01*
+%TO.N,/UART1_5V_EN*%
+X133160000Y-71500000D02*
+X133550000Y-71110000D01*
+X132000000Y-71500000D02*
+X133160000Y-71500000D01*
+%TO.N,/UART1_RX*%
+X154084738Y-82242187D02*
+X154375000Y-81951925D01*
+X154375000Y-81951925D02*
+X154375000Y-79802500D01*
+X154375000Y-79802500D02*
+X153562500Y-78990000D01*
+%TO.N,/UART1_5V_EN*%
+X199330000Y-72500000D02*
+X192000000Y-72500000D01*
+X201580000Y-70250000D02*
+X199330000Y-72500000D01*
+X201580000Y-69250000D02*
+X201580000Y-70250000D01*
+%TO.N,/I2C_SDA*%
+X187000000Y-87207000D02*
+X187293000Y-87500000D01*
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+X155500000Y-90500000D01*
+%TO.N,/OUT12_3V3*%
+X190170000Y-77365000D02*
+X187135000Y-77365000D01*
+X187135000Y-77365000D02*
+X185437500Y-79062500D01*
+X185437500Y-79062500D02*
+X185437500Y-91555000D01*
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